Spezifikationen für PCB-Design-Services sind solche

Gepostet am 2020-03-03

DRC-Systemansatz (Pcb Design Rule Checker). Nachdem Sie das Tool zur Erstellung von Schaltplänen verwendet haben, um das PCB-Design zu erhalten, können Sie DRC ausführen, um Fehler zu finden, die gegen die PCB-Designregeln verstoßen. Diese Vorgänge müssen abgeschlossen sein, bevor die nachfolgende Verarbeitung beginnen kann, und Entwickler von Schaltkreiserzeugungswerkzeugen müssen DPCB-Werkzeuge bereitstellen, die die meisten Leiterplattenentwickler problemlos beherrschen können.

There are many advantages to writing your own PCB design rule checker. Although the PCB design checker is not so simple, it is not unattainable, because any PCB designer who is familiar with existing programming or scripting languages ​​can fully The benefits of work are incalculable.

However, general purpose marketing tools are often not flexible enough to meet specific PCB design needs. Therefore, customers must reflect the new feature requirements to the DRC tool developers, and this usually takes a certain amount of money and time, especially when the requirements are constantly updated. Fortunately, most tool developers can provide customers with a convenient way to write their own DRC to meet specific needs. However, this powerful tool has not been widely recognized or used. This article provides a practical guide to getting the most out of your DRC tools.

Since the DRC must traverse the entire circuit design of the PCB, including each symbol, each pin, each network, and each attribute, if necessary, an unlimited number of “accessory” files can be created. As described in Section 4.0, DRC can flag any minor deviations that violate PCB design rules. For example, one of the accompanying documents may contain all the decoupling capacitors used in the PCB design. If the number of capacitors is lower or higher than the expected value, a red mark will be marked where the power line dv / dt problem may occur. These ancillary files may be necessary, but not any commercial DRC tool will necessarily create them.

Another advantage of DRC is that it is easy to update to meet the needs of new PCB design characteristics, such as those that may affect PCB design rules. And, once you have sufficient experience in this area, there are many other functions that can be implemented.

For example, if you can write your own DRC, you can write your own bill of materials (BOM) creation tool, which can better handle specific user needs, such as how to obtain “extra hardware” for devices that are not part of the circuit diagram database (such as Socket, heat sink, or screwdriver). Or PCB designers can write their own Verilog netlist analyzer, which has sufficient flexibility in the PCB design environment, such as how to obtain Verilog models or time files suitable for a specific device. In fact, because DRC traverses the entire PCB design circuit diagram, it can collect all valid information to output the simulation and / or BOM required for PCB design Verilog netlist analysis.

It is a bit far-fetched to discuss these topics without providing any program code. For this reason, we will use a circuit diagram acquisition tool as an example. This article uses the ViewDraw tool developed by Mentor Graphics, a subsidiary of the PADS-Designer product line. In addition, we also use the ViewBase tool, which is a simplified C routine library that can be called and accesses the ViewDraw database. With ViewBase tools, PCB designers can easily use C / C language to write complete and efficient DRC tools for ViewDraw [2] [3]. Note that the basic principles discussed here apply equally to any other PCB schematic tool.

Input file

In addition to the circuit diagram database, DRC also needs some input files that can describe specific situations, such as legal power network names that are automatically connected to the power plane. For example, if the power network is named POWER, the power plane will be automatically connected to the power plane using back-end packaging equipment (such as for ViewDrawpcbfwd). A list of input files is given below. These files must be placed in a fixed global location so that DRC can automatically find and read them, and then save this information inside the DRC at runtime.

Some symbols must have external power line pins because these symbols are not connected to the regular power line layer. For example, the ECC device’s VCC pin can either be connected to VCC or GROUND; its VEE pin can be connected to GROUND or -5.0V plane. In addition, the power line pins can be connected to the filter before reaching the power line layer.

The power line pins are usually not externally connected to the device symbol. Instead, an attribute of the symbol (herein referred to as SIGNAL) describes which pin is a power pin or a ground pin and describes that the pin should be connected to a network name.



Der DRC kann dieses Attribut lesen und sicherstellen, dass der Netzwerkname in der Datei legal_pwr_net_name gespeichert ist. Wenn der legal_pwr_net_name nicht den Netzwerknamen enthält, wird der Power-Pin nicht mit der Power-Ebene verbunden, und dieses Problem ist wirklich schwerwiegend.

Die Datei legal_pwr_net_name ist optional. Diese Datei enthält alle zulässigen Netzwerknamen des POWER-Signals, z. B. VCC, V3_3P und VDD. Im PCB-Layout / Routing-Tool muss der Fall des Namens unterschieden werden. Im Allgemeinen ist VCC nicht dasselbe wie Vcc oder vcc. VCC kann ein 5,0-V-Netzteil sein, während V3_3P ein 3,3-V-Netzteil sein kann.

Die Datei legal_pwr_net_name ist optional, da die Konfigurationsdatei für das Back-End-Paket normalerweise eine Reihe von zulässigen Netzwerknamen für Netzkabel enthalten muss. Wenn Sie das Allegro-Verkabelungstool von CadencePCB Design System verwenden, lautet der Dateiname pcbfwd allegro.cfg und weist die folgenden Eingabeparameter auf:


Stromversorgung: VCC VDD VEE V3_3P V2_5P 5V 12V

Wenn der DRC die Datei allegro.cfg anstelle von legal_pwr_net_name direkt lesen kann, werden bessere Ergebnisse erzielt (dh die Wahrscheinlichkeit, Fehler einzuführen, ist geringer).