Как разработать многослойную печатную платуОпубликовано 2020-07-09
При разработке многослойной печатной платы одним из важных моментов является планирование многослойного стека печатных плат для достижения наилучших характеристик продукта. Плохо спроектированные подложки и неправильный выбор материалов снизят электрические характеристики передачи сигнала, увеличат эмиссию и перекрестные помехи, а также сделают продукт более восприимчивым к внешним шумам. Эти проблемы могут привести к прерывистой работе, так как временные сбои и помехи значительно снизят производительность и долгосрочную надежность продукта.
Multilayer PCB stackup
In contrast, a properly constructed PCB circuit board substrate can effectively reduce electromagnetic radiation, crosstalk, and improve signal integrity, thereby providing a low-inductance distribution network. Moreover, from a manufacturing point of view, the manufacturability of the product can also be improved.
The plane in the multilayer PCB can significantly reduce the radiated emissions on the two-layer печатная плата. According to experience, the radiation of the four-layer board will be reduced by 15 dB compared to the double-sided PCB board.
When choosing a multilayer PCB stack, we should consider the following factors:
- The signal layer should always be adjacent to the plane. This limits the number of signal layers embedded between planes to two and the top and bottom (outer) layers to one signal.
- Сигнальный слой должен быть плотно связан (<10 MIL) с прилегающей к нему плоскостью.
- Плоскость питания (и земля) может использоваться для обратного пути сигнала.
- Определите обратный путь сигнала (какая плоскость будет использоваться).
- Сигналы с быстрым нарастанием используют путь наименьшей индуктивности, обычно ближайшую плоскость.
- Стоимость (важнейший параметр дизайна).
1. Паяльная маска - влияние на импеданс
Поскольку печатные платы обычно покрыты паяльными масками, при расчетах следует учитывать влияние импеданса конформного покрытия. Как правило, паяльная маска снижает полное сопротивление тонкой дорожки на 2–3 Ом. Чем больше толщина дорожки, тем меньше эффект паяльной маски.
2. Влияние покрытия паяльной маски.
The figure above illustrates the effect of solder mask coating on microstrip impedance. This example is a commonly used liquid photoimageable solder mask with a thickness of 0.5 MIL and a dielectric constant of 3.3.
The solder mask reduces the characteristic impedance of the microstrip by 2 ohms. The differential impedance is 3.5 ohms. Therefore, if you do not consider solder masks, the calculation may exceed 3% to 4%.
3. Dielectric material
The most popular dielectric material is FR4, which can be a core material or prepreg (prepreg) material.
The core material is a thin dielectric (cured glass fiber epoxy resin), and copper foil is bonded to both sides. For example: Isola’s FR406 material-including 5, 8, 9.5, 14, 18, 21, 28, 35, 39, 47, 59 and 93 MIL cores. The thickness of copper is usually ½ to 2 ounces (17 to 70 microns).
The prepreg material is a glass fiber sheet impregnated with uncured epoxy resin, which hardens when heated and pressed during the производства печатной платы process. Isola’s FR406 materials-including 1.7, 2.3, 3.9 and 7.1 MIL prepregs, can be combined to achieve the desired prepreg thickness.
The most common stack is called the “foil method” which is a prepreg with copper foil-bonded to the outside on the outermost layers (top and bottom) and then alternated with the prepreg throughout the substrate. The other overlay is called the “encryption method”, which is the opposite of the foil method and is used by old-school military contractors.
Let’s take a look at the most common multi-layer configuration.
4-layer PCB stackup
A typical four-layer board stackup is shown below. Calculate substrate characteristics and differential impedance.
It is common to see four-layer boards stacked evenly. That is, the four evenly spaced layers, with the plane in the center. Although this does make the board symmetrical, it does not help EMC.
In addition, another common mistake is to make the plane tightly coupled to the large dielectric layer and plane between the center and the signal. This will definitely produce good inter-plane capacitance, but it also does not help signal integrity, crosstalk or EMC-this is why we chose to use a 4-layer PCB on two layers.
To improve the EMC performance of capacitors, it is best to place the signal layer as close as possible to the plane (<10 MIL), and use a large core (~40 MIL) between the power and ground planes to maintain the overall substrate thickness ~62 MIL. Close tracking of planar coupling will reduce crosstalk between traces and allow us to keep the impedance at an acceptable value.
A good impedance range (Zo) is 50 to 60 ohms. Keep in mind that lower impedance will increase dI/dt and significantly increase the current drawn (not good for PDN), higher impedance will emit more EMI, and make the design more susceptible to interference from outside influences.
6-layer PCB stackup
The six-layer board is basically a four-layer board with two additional signal layers added between the planes. This greatly improves EMI because it provides two buried layers for high-speed signals and two surface layers for routing low-speed signals.
The plate thickness (62 MIL) consists of a thicker central core. There is always a trade-off between trace impedance, trace width, and prepreg/core thickness, and it is best to use Rayming recommendations to provide a quick “what-if” analysis. Rayming Stackup Planner calculates characteristic impedance plus edge-coupled and broad-side coupled differential impedance. The latter applies only to embedded dual stripline layers. Differential pairs are becoming more and more common in high-speed designs, using differential mode signals to reduce noise.
8-layer PCB stackup
To improve EMC performance, add two more planes in the six-layer stack. It is recommended not to have more than two adjacent signal layers between the planes, as this will create impedance discontinuities (the signal layer impedance difference is ~20 ohms) and increase the crosstalk between these signal layers.
In the following case, two planar layers are added to the center of the substrate. This allows tight coupling between the center planes and isolates each signal plane, thereby reducing coupling and thereby significantly increasing crosstalk. This configuration is commonly used for high-speed signals in DDR2 and DDR3 designs, where crosstalk due to tight wiring is a problem.
10-layer PCB stackup
When six wiring layers and four planes are required, a ten-layer board should be used-and EMC deserves attention.
The above demonstrates a typical 10-layer layer overlay. This superposition is ideal because of the tight coupling of the signal and return planes, the shielding of high-speed signal layers, the presence of multiple ground planes, and the tightly coupled power/ground plane pair in the center of the board. High-speed signals are usually routed on signal layers buried between planes (3-4 layers and 7-8 layers in this case). However, care should be taken to properly route these signals. Others, avoid coupling (crosstalk) between adjacent layers.
12-layer PCB stackup
12 layers is the maximum number of layers that can usually be easily manufactured in 62MIL thick plates. Occasionally you will see 14 to 16 layers of circuit boards made of 62MIL thick circuit boards, but the number of manufacturers that manufacture them is limited to those who can produce HDI circuit boards.
High-level counting boards (more than a dozen) require thin dielectrics (usually 5MIL or less on 62MIL thick boards), so they are automatically tightly coupled.
With proper stacking and wiring, they can meet all our high-speed requirements and will have excellent EMC performance and signal integrity. The above twelve layers provide shielding on six inner layers.
Determine the number of layers
The technical rules are based on the minimum pitch of the SMT components used, which is basically the largest trace, clearance and through holes allow, while minimizing PCB manufacturing costs. Complex high-speed designs using ball grid arrays (BGA) usually require 4/4 MIL (trace/gap) and 20/8 MIL (pad/hole) via technologies. However, if required, use a lower size, which will reduce costs and increase manufacturing yield.
Once these rules are established, calculate the required characteristic impedance (Zo) and the required superimposition (Zdiff) according to the component data sheet. Generally, 50 Ohm Zo and 100 Ohm Zdiff are used. Keep in mind that lower impedance will increase dI/dt and significantly increase the current drawn (unfavorable to PDN), and higher impedance will generate more EMI and make the design more susceptible to external interference. Therefore, a good Zo range is 50-60 ohms.